Export Control List (SOR/89-202)

AMENDMENTS NOT IN FORCE

• — SOR/2024-112, s. 1

  • 1 Subitem 5504(1) of the schedule to the English version of the Export Control ListFootnote ¹ is replaced by the following:

    • Return to footnote ¹SOR/89-202; SOR/2009-128, s.1

    • 5504

      • (1) In this item, development, production, software, spacecraft, technology and use have the same meaning as in the provision of the Guide entitled “Definitions of Terms Used in Groups 1 and 2”.

• — SOR/2024-112, s. 2

  • 2 Group 5 of the schedule to the List is amended by adding the following after item 5505:

    Other Strategic Goods and Technology (All Destinations Other than the United States)

    • 5506

      • (1) In this item, development, electronic assembly, Gate-All-Around Field-Effect Transistor (GAAFET), production, software, technology and use have the same meaning as in the provision of the Guide entitled “Definitions of Terms Used in Groups 1 and 2”.

      • (2) Other strategic goods and technology as follows:

        • (a) subject to the “General Software Note” in Group 1 of the Guide, software, other than that referred to in Group 1 of the Guide, as follows:

          • (i) software specially designed or modified for the development or production of items specified in clause (c)(ii)(B) or (C) or subparagraph (d)(iii) or (iv),

          • (ii) software specially designed for the use of items specified in subparagraph (d)(iii), and

          • (iii) software designed to extract Graphic Design System II (GDSII) or equivalent standard layout data and perform layer-to-layer alignment from Scanning Electron Microscope (SEM) images, and to generate multi-layer GDSII data or the circuit netlist;

            • NOTE

              In subparagraph (iii), Graphic Design System II (GDSII) means a database file format for the data exchange of integrated circuit artwork or integrated circuit layout artwork.

        • (b) subject to the “General Technology Note” in Group 1 of the Guide, technology, other than that are referred to in Group 1 of the Guide, as follows:

          • (i) technology specially designed or modified for the development or production of items specified in clause (c)(ii)(B) or (C) or subparagraph (d)(iii)or (iv), and

          • (ii) technology specially designed or modified for the development or production of integrated circuits or of devices, using Gate-All-Around Field-Effect Transistor (GAAFET) structures;

            • NOTE

              1 Subparagraph (ii) includes process recipes. Process recipe means a set of conditions and parameters for a particular process step.

              2 Subparagraph (ii) does not apply to technology used for tool qualification or maintenance.

        • (c) systems, equipment and components, other than those referred to in Group 1 of the Guide, as follows:

          • (i) Complementary Metal Oxide Semiconductor (CMOS) integrated circuits designed to operate at an ambient temperature equal to or less (better) than 4.5 K (-268.65°C),

            • NOTE

              For the purposes of subparagraph (i), Complementary Metal Oxide Semiconductor (CMOS) integrated circuits can also be referred to as cryogenic CMOS or cryoCMOS.

          • (ii) quantum computers and related electronic assemblies and components therefor, as follows:

            • (A) quantum computers, as follows:

              • (I) quantum computers supporting 34 or more, but fewer than 100, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 10^-4,

              • (II) quantum computers supporting 100 or more, but fewer than 200, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 10^-3,

              • (III) quantum computers supporting 200 or more, but fewer than 350, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 2 x 10^-3,

              • (IV) quantum computers supporting 350 or more, but fewer than 500, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 3 x 10^-3,

              • (V) quantum computers supporting 500 or more, but fewer than 700, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 4 x 10^-3,

              • (VI) quantum computers supporting 700 or more, but fewer than 1,100, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 5 x 10^-3,

              • (VII) quantum computers supporting 1,100 or more, but fewer than 2,000, fully controlled, connected and working physical qubits, and having a C-NOT error of less than or equal to 6 x 10^-3, and

              • (VIII) quantum computers supporting 2,000 or more fully controlled, connected and working physical qubits,

            • (B) qubit devices and qubit circuits, containing or supporting arrays of physical qubits, and specially designed for items specified in clause (A), and

            • (C) quantum control components and quantum measurement devices specially designed for items specified in clause (A);

            • NOTE

              1 Items in clause (B) include semiconductor, superconducting and photonic qubit chips and chip arrays, surface ion trap arrays, other qubit confinement technology, and coherent interconnects between such items.

              2 Clause (C) applies to items designed for calibrating, initializing, manipulating or measuring the resident qubits of a quantum computer.

              3 Subparagraph (ii) applies to circuit model (or gate-based) and one-way (or measurement-based) quantum computers but does not apply to adiabatic (or annealing) quantum computers.

              4 Items specified in subparagraph (ii) may not necessarily physically contain any qubits. For example, quantum computers based on photonic schemes do not permanently contain a physical item that can be identified as a qubit. Instead, photonic qubits are generated while the computer is operating and then later discarded.

              5 In subparagraph (ii), physical qubit means a two-level quantum system used to represent the elementary unit of quantum logic by means of manipulations and measurements that are not error-corrected. Physical qubits are distinguished from logical qubits, in that logical qubits are error-corrected qubits composed of many physical qubits.

              6 In clause (A), supporting 34 or more fully controlled, connected, working physical qubits refers to the capability of a quantum computer to confine, control, measure and process the quantum information embodied in 34 or more physical qubits.

              7 In clause (A), fully controlled means that the physical qubit can be calibrated, initialized, gated and read out, as necessary.

              8 In clause (A), connected means that two-qubit gate operations can be performed between any arbitrary pair of the available working physical qubits. This does not necessarily entail all-to-all connectivity.

              9 In clause (A), working means that the physical qubit performs universal quantum computational work according to the system specifications for qubit operational fidelity.

              10 In clause (A), C-NOT error means the average physical gate error for the nearest-neighbour two-physical qubit Controlled-NOT (C-NOT) gates.

        • (d) test, inspection and production equipment, other than that referred to in Group 1 of the Guide, as follows:

          • (i) masks and reticles designed for integrated circuits specified in subparagraph (c)(i),

          • (ii) imprint lithography templates designed for integrated circuits specified in subparagraph (c)(i),

          • (iii) equipment designed for dry etching, as follows:

            • (A) equipment designed or modified for isotropic dry etching and having a largest silicon-germanium to silicon (SiGe:Si) etch selectivity greater than or equal to 100:1, or

              • NOTE

                For the purposes of clause (A), silicon-germanium to silicon (SiGe:Si) etch selectivity is measured for a germanium (Ge) concentration of greater than or equal to 30% (Si_0.70Ge_0.30).

            • (B) equipment designed or modified for anisotropic dry etching, and having all of the following:

              • (I) one or more Radio Frequency (RF) power sources with at least one pulsed Radio Frequency (RF) output,

              • (II) one or more fast gas switching valves with a switching time of less than 300 ms,

              • (III) an electrostatic chuck with 20 or more individually controllable variable temperature elements, and

              • NOTE

                1 Clause (B) includes etching using Radio Frequency (RF) pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, or cyclic injection and purging of gases combined with a plasma; plasma atomic layer etching; and plasma quasi-atomic layer etching.

                2 Subparagraph (iii) includes etching by radicals, ions, sequential reactions, or non-sequential reaction.

                3 In note 2, radical means an atom, molecule, or ion that has an unpaired electron in an open electron shell configuration.

          • (iv) Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, and having all of the following:

            • (A) a stage placement accuracy less (better) than 30 nm,

            • (B) a stage positioning measurement performed using laser interferometry,

            • (C) a position calibration within a Field-of-View (FOV) based on laser interferometer length-scale measurement,

            • (D) a collection and storage of images with more than 2 x 10⁸ pixels,

            • (E) a Field-of-View (FOV) overlap of less than 5% in vertical and horizontal directions,

            • (F) a Field-of-View (FOV) stitching overlap of less than 50 nm, and

            • (G) an accelerating voltage of more than 21 kV.

            • NOTE

              1 Subparagraph (iv) includes Scanning Electron Microscope (SEM) equipment designed for chip design recovery.

              2 Subparagraph (iv) does not apply to Scanning Electron Microscope (SEM) equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).